Alternate Display Driver

The purpose of this entry is to describe the assembly,  programming and testing of the alternate Clock Display Module - whereby instead of a dedicated display driver chip, the module will be controlled by its own micro controller. This was created under a separate GitHub branch as UCtl_small. After the relative ease of getting the … Continue reading Alternate Display Driver

MAX7221 Driven Display Module

It is now time to put some theory into action. This entry will talk about the implementation of the clock display module driven by the MAX7221. This chip was selected for the first version of the display module as it provided a one-stop solution for driving seven segment displays. It also SPI compatible and provided some additional features like … Continue reading MAX7221 Driven Display Module

Display Revisited

While waiting for the display board to return from OSHPark, I was also interested in an alternative module. I had mentioned this idea before and it was time to start taking a closer look. For the purpose, I created another branch in GitHub rather than creating a whole new project. The key feature of this … Continue reading Display Revisited

Back to the Drawing Board

Well, not exactly back to the drawing board for everything... What has developed since doing the actual schematic is that the display module was treated as a black box. Now it is time to open this up and understand how this is to work. The beauty of this approach is that not knowing anything about … Continue reading Back to the Drawing Board

Wired for Action – almost

In the last post, I presented the initial ideas for powering the project. Now it is time to move on and start looking into the individual modules. I was impressed as to how quickly this part progressed since I had done the up-front thinking of the pin and port allocation. So much so, that before … Continue reading Wired for Action – almost

Module One – Power On!

In the last post, the basic device was layed out in terms of requirements, block diagram and a state machine. It is clearly not 100% complete but I don't believe that the whole project should be blocked, trying to model absolutely everything. As the project develops and matures, issues will be encoutered and design decisions … Continue reading Module One – Power On!

Modelling First

I have mentioned about the re-working of an old alarm clock. In this post, I will be kicking the project off and introducing my efforts to model the requirements and project organisation in SysML. I will be using Systems Architect from Sparx Systems. Project Organisation The project organisation shows the directory structure of the project … Continue reading Modelling First